Means for dividing input clock frequencies by even numbers are generally known. Using these means, a desired 50% duty cycle can be achieved. By duty cycle, there is meant the ratio of the time for which a signal is "high" to the time it is "low" in one cycle i.e. for a 50% duty cycle a signal is "high" 50% of the time i.e. the mark-to-space ratio is unity.
Dividing frequencies by odd numbers is known and various means of such division exist. However, the means of the prior art are usually encumbered with the restriction that the duty cycle of the output signal is not 50%, but it is above or below 50% by at least one clock cycle of the input frequency or it is asynchronous. One such solution is presented in the European Patent Application, Publication No. 247,769. If the ratio R between the input clock frequency and the output clock frequency is relatively low i.e. less than 11 to 15, a programmable counter with a duty cycle of 1/R can be used for frequency division when the input clock frequency is less than 10 MHz. If the ratio R is high, the input clock frequency must be relatively low, 1 to 2 MHz at most. In both instances the duty cycle is 1/R unless additional decoding logic is used.
When the ratio R is high, several consecutive dividers, or counters, can be used for frequency division. If the counters act synchronously, i.e. the clock inputs of the flip-flops of the counters are connected directly to the same clock so that no propagation delays arise, the duty cycle is always 1/R. The desired frequency can also be generated by adding a completely new frequency into the system. An extra local oscillator is, however, required in such instances.
Another problem has been, that to date it has been difficult to get the output signal synchronized. The output signal is often expected to be symmetrical, and for instance, in order to exclude any phase jitter or other distortions, at least the leading edges should be evenly spaced, as should also the trailing edges. No generally known appropriate means exist for this purpose.
Division with odd numbers has generally been abandoned. A great number of oscillators of different frequencies have been adopted. This involves extra component costs.
In addition to dividing by odd numbers there is often a need to divide by decimal numbers. One such implementation is presented in the U.S. Pat. No. 4,935,944, but this solution has the drawback that the circuit includes feedback loops, which cause delays.